International Conference on Information and Knowledge Technology

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Low-Power Phase-Based Stochastic MAC for FPGA

Authors :

Kooroush Manochehri¹ Amir arsalan Sakhtianchi² Mehrshad Khosraviani³

1- دانشگاه امیرکبیر 2- دانشگاه امیرکبیر 3- دانشگاه امیرکبیر

Keywords :

stochastic computing،multiply–accumulate (MAC)،Phase Generator،FPGA Implementation،Low-Power Design

Abstract :

This paper presents a low-power stochastic multiply–accumulate (MAC) engine optimized for FPGA deployment. The design introduces a deterministic phase generator that replaces conventional random number generators with decorrelated unary bitstreams, achieving statistical independence with minimal logic overhead. Using coprime n-bit counters, programmable phase offsets, and bit-reversal transforms, the architecture attains near fixed-point accuracy through lightweight shift–add logic and compact counters. Evaluations on 8×8, 14×14, 16×16, and 28×28 bipolar dot-product configurations show strong correlation with exact arithmetic and superior efficiency over conventional stochastic and binary MACs. Synthesized on a Xilinx Artix-7 FPGA, the implementation achieves up to 67% LUT and 68% flip-flop reductions, along with 50–80% power savings, validated through a synthesizable VHDL prototype. Cycle-accurate simulations confirm exact results for ∣x∣≤7with gain = 16, maintaining low error across wider ranges. The proposed phase-driven decorrelation method effectively eliminates inter-stream correlation, enabling fixed-point-like precision with high area and energy efficiency in FPGA-based stochastic hardware.